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Clock Generation and Distribution

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	Clock Generation and Distribution

Description

Analog Devices offers ultra-low jitter clock distribution and clock generation products for wireless infrastructure, instrumentation, broadband, ATE and other applications demanding sub picosecond performance. ADI clock products deliver low jitter, low phase noise, and low spurs making them ideal for clocking high performance analog-to-digital converters (ADCs) and digital-to-analog converters (DACs). ADI clock ICs integrate PLL cores, dividers, phase offset, skew adjust, and clock drivers in small chip scale packages. (An Overview of the Clock Distribution/Generation Family is available.)

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ADIsimCLK reference designs are also available.

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Last Updated: 10/2006

Part #	Clock Function	Added Features	Voltage Supply (V)	Max Input Frequency (MHz)	No. of Outputs	Max Output Frequency (MHz)	Output Logic	Random Jitter (ps rms)	I/O Interface	Package	1K Price ($US)
AD9510	Clean-Up Generation Distribution	2 Delay Lines	3.3	1600	8	1200	LVPECL, LVDS, CMOS	0.25 additive	Serial	64-LFCSP	11.95
AD9511	Clean-Up Generation Distribution	1 Delay Line	3.3	1600	5	1200	LVPECL, LVDS, CMOS	0.25 additive	Serial	48-LFCSP	9.95
AD9512	Division Distribution	1 Delay Line	3.3	1600	5	1200	LVPECL, LVDS, CMOS	0.25 additive	Serial	48-LFCSP	8.95
AD9513	Division Distribution	1 Delay Line	3.3	1600	3	800	LVDS, CMOS	0.3 additive	Pin Select	32-LFCSP	5.95
AD9514	Division Distribution	1 Delay Line	3.3	1600	3	1600	LVPECL, LVDS, CMOS	0.225 additive	Pin Select	32-LFCSP	5.95
AD9515	Division Distribution	1 Delay Line	3.3	1600	2	1600	LVPECL, LVDS, CMOS	0.225 additive	Pin Select	32-LFCSP	4.75
AD9516-0	Clean-Up Generation Distribution	2.8G VCO, 4 Delay Lines	3.3	2400	14	2950	LVPECL, LVDS, CMOS	< 0.5 total	Serial	64-LFCSP	12.50
AD9516-1*	Clean-Up Generation Distribution	2.5G VCO, 4 Delay Lines	3.3	2400	14	2650	LVPECL, LVDS, CMOS	< 0.5 total	Serial	64-LFCSP	12.50
AD9516-2*	Clean-Up Generation Distribution	2.2G VCO, 4 Delay Lines	3.3	2400	14	2350	LVPECL, LVDS, CMOS	< 0.5 total	Serial	64-LFCSP	12.50
AD9516-3*	Clean-Up Generation Distribution	2.0G VCO, 4 Delay Lines	3.3	2400	14	2200	LVPECL, LVDS, CMOS	< 0.5 total	Serial	64-LFCSP	12.50
AD9516-4*	Clean-Up Generation Distribution	1.8G VCO, 4 Delay Lines	3.3	2400	14	1900	LVPECL, LVDS, CMOS	< 0.5 total	Serial	64-LFCSP	12.50
AD9540	Clean-Up Generation	2.7G PLL Core, 48-B DDS	1.8, 3.3	655	1	655	CML, PECL- compatible	0.7 total	Serial	48-LFCSP	9.95