Products and Solutions ---------- SOLUTIONS ---------- Galaxy Design Platform ? Timing Closure Solution ? Signal Integrity Solution ? Test Solution ? Power Solution Discovery Verification Platform ? System Analysis & Design ? Smart RTL Verification ? Functional Equivalence Checking ? Mixed-Signal ? Languages Intellectual Property (IP) ? DesignWare Library ? DesignWare Verification IP ? DesignWare Cores ? DesignWare Star IP ? DesignWare SystemC Libraries Design for Manufacturing ? mask synthesis ? lithography verification ? Mask Data Preparation ? TCAD ? Manufacturing Equipment Professional Services ? Technology Consulting ? Flow Optimization ? Design Realization ? IP Integration ? Concept to Parts ? Core Hardening ---------- PRODUCTS ---------- Af-Gen: Assist feature generation Apollo II: Place and route Astro: Physical implementation Astro-Rail: Reliability analysis Aurora: Device characterization BSD Compiler: Test synthesis Cadabra: Cell creation CATS: Mask data preparation CosmosLE: Layout design environment CosmosScope: Waveform analysis CosmosSE: Schem. design environment Circuit Explorer: AMS optimization DC Expert: RTL synthesis DC FPGA: FPGA synthesis DC Ultra: RTL synthesis Design Analyzer: RTL synthesis Design Compiler: RTL synthesis Design Vision: RTL synthesis DesignWare: Design & verif. IP DFT Compiler: Test synthesis Discovery AMS: Mixed-signal Encore: Packaging Enterprise: Layout editor ESP: Functional Equivalence Checking Formality: Funct. equiv. checking HDL Compiler: RTL synthesis Hercules: Physical verification HSPICE: Accurate circuit simulation i-Virtual Stepper: Mask qualification iN-Phase: Phase shift mask JupiterXT: Design planning Leda: RTL checker Libra-Passport: Physical library Libra-Visa: Physical library Library Compiler: Library compilation Magellan: RTL formal verification Milkyway: Design database Module Compiler: Datapath synthesis NanoSim: Fast circuit simulation PathMill: Transistor-level STA Physical Compiler: Physical synthesis PowerMill: Circuit simulation Power Compiler: Power optimization PrimePower: Power analysis PrimeTime: Static timing analysis PrimeTime SI: Signal integrity analysis ProGen: Litho. model creation Proteus: Optical prox. correction Saber: Multi-tech. simulation Scirocco: VHDL simulation SiVL-LRC: Lithography verification Star-MTB: Cell characterization Star-RCXT: Full-chip RC extraction Star-SimXT: Fast circuit simulation System Studio: System-level verification Taurus: Process simulation TetraMAX: ATPG TimeMill: Circuit simulation VCS: HDL simulation VCS MX: Mixed-HDL simulation Vera: Testbench automation

more...      01/2005 European Mask & Lit.  Conference  02/2005 DVCon 2005  San Jose, CA  02/2005 SPIE Microlithography  Symposium  03/2005 DATE 2005 Munich, Germany  03/2005 SNUG San Jose  Register Today!